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參數(shù)資料
| 型號： | CY7C138 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x 8 Dual-Port Static RAM(4K x 8 雙端口靜態(tài) RAM) |
| 中文描述： | 4K的× 8雙端口靜態(tài)存儲器（4K的× 8雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 277K |
| 代理商： | CY7C138 |
4K x 8/9 Dual-Port Static RAM
CY7C138
CY7C139
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 1996
Features
True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
4K x 8 organization (CY7C138)
4K x 9 organization (CY7C139)
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: I
CC
= 160 mA (max.)
Fully asynchronous operation
Automatic power-down
TTL compatible
Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Available in 68-pin PLCC
Functional Description
The CY7C138 and CY7C139 are high-speed CMOS 4K x 8
and 4K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C138/9 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9
can be utilized as a standalone 8/9-bit dual-port static RAM or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 16/18-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications sta-
tus buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
Notes:
1.
2.
BUSY is an output in master mode and an input in slave mode.
Interrupt: push-pull output and requires no pull-up resistor.
C138-1
R/W
L
CE
L
OE
L
A
11L
A
0L
A
0R
A
11R
R/W
R
CE
R
OE
R
I/O
7L
I/O
0L
7R
I/O
0R
INTERRUPT
SEMAPHORE
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
SEM
L
INT
L
SEM
R
INT
R
BUSY
L
BUSY
R
M/S
(7C139)I/O
8L
I/O
8R
(7C139)
Logic Block Diagram
[2]
[2]
[1, 2]
[1, 2]
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C139 | 4K x 9 Dual-Port Static RAM(4K x 9 雙端口靜態(tài) RAM) |
| CY7C1399-12VI | 32K x 8 3.3V Static RAM |
| CY7C1399-15ZI | 32K x 8 3.3V Static RAM |
| CY7C1399-20VI | 32K x 8 3.3V Static RAM |
| CY7C1399-25VC | 32K x 8 3.3V Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C1380B-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 4.2ns 100-Pin TQFP |
| CY7C1380B-133AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 4.2ns 100-Pin TQFP |
| CY7C1380B-133BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 18MBIT 512KX36 4.2NS 165FBGA - Bulk |
| CY7C1380B-150AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1380B-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 3.4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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