參數(shù)資料
型號: CY7C1387D-200BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
中文描述: 1M X 18 CACHE SRAM, 3 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 9/30頁
文件大?。?/td> 974K
代理商: CY7C1387D-200BZXC
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Document Number: 38-05545 Rev. *E
Page 9 of 30
Truth Table
[4, 5, 6, 7, 8]
Operation
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
H
L
L
L
L
X
L
L
L
L
L
X
X
H
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
H
X
H
X
L
L
L
L
L
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
H
H
H
H
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
X
X
X
X
X
X
L
H
X
L
H
L
H
L
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
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