參數(shù)資料
型號(hào)： CY7C1387D-200BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
中文描述： 1M X 18 CACHE SRAM, 3 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 8/30頁
文件大小： 974K
代理商： CY7C1387D-200BZI
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Document Number: 38-05545 Rev. *E
Page 8 of 30
The write signals (GW, BWE, and BW
X
) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
x
inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BW
X
signals.
The
provides byte write capability that is described in the write
cycle description table. Asserting the byte write enable input
(BWE) with the selected byte write input, will selectively write
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self
timed write mechanism has been provided to simplify the write
operations.
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
common IO device, the output enable (OE) must be
deasserted HIGH before presenting data to the DQ
inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQ are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BW
X
) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQ
X
is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self
timed write mechanism has been provided to simplify the write
operations.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
common IO device, the output enable (OE) must be
deasserted HIGH before presenting data to the DQ
X
inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQ
X
are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
provides a two-bit wraparound counter, fed by A
[1:0]
, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CEs, ADSP, and ADSC must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
A1: A0
00
01
01
10
10
11
11
00
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
Max
80
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
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