參數(shù)資料
型號(hào)： CY7C1387C-225BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
中文描述： 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
封裝： 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
文件頁(yè)數(shù)： 11/34頁(yè)
文件大?。?/td> 554K
代理商： CY7C1387C-225BZC
CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 11 of 34
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386C/CY7C1387C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
X
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE
1
, CE
2
, CE
3[2]
and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
co
if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
The CY7C1386C/CY7C1387C is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will tri-state
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW
X
) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
x
inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW
X
signals. The CY7C1386C/CY7C1387C provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1386C/CY7C1387C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ
inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW
) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQ
X
is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1386C/CY7C1387C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ
X
inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ
X
are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1386C/CY7C1387CCY7C1387C provides a two-bit
wraparound counter, fed by A
[1:0]
, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
相關(guān)PDF資料
PDF描述
CY7C1386C-167BG 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BZI 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-200AC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1387D-167AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1387D-167AXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1387D-167AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1387D-167BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb (1Mb x 18) 靜態(tài)隨機(jī)存取存儲(chǔ)器 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C138XC 制造商:Cypress Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*