參數(shù)資料
型號(hào)： CY7C1386C-225BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
中文描述： 512K X 36 CACHE SRAM, 2.8 ns, PBGA165
封裝： 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
文件頁(yè)數(shù)： 16/34頁(yè)
文件大?。?/td> 554K
代理商： CY7C1386C-225BZC
CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 16 of 34
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the operating Range
[10, 11]
Parameter
Symbol
Min
Max
Units
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
t
TCYC
t
TF
t
TH
t
TL
100
ns
MHz
ns
ns
10
40
40
t
TDOV
t
TDOX
20
ns
ns
0
t
TMSS
t
TDIS
t
CS
10
10
10
ns
ns
t
TMSH
t
TDIH
t
CH
10
10
10
ns
ns
ns
Notes:
10.
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1ns.
相關(guān)PDF資料
PDF描述
CY7C1387C-225BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BG 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BZI 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1386D-167AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1386D-167AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1386D-200AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1386D-200AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1386D-200BGCT 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 3NS 119BGA - Tape and Reel
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