參數(shù)資料
型號(hào): CY7C1386C-200AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
中文描述: 512K X 36 CACHE SRAM, 3 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù): 13/34頁(yè)
文件大?。?/td> 554K
代理商: CY7C1386C-200AC
CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 13 of 34
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
WRITE Cycle,Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle,Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
and CE
2
.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW
X
is valid Appropriate write will be done based on which byte write is active.
Partial Truth Table for Read/Write
[5, 9]
Function (CY7C1386C)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BW
D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW
C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW
B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BW
A
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write Bytes B, A
Write Byte C – ( DQ
C
and DQP
C
)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQ
D
and DQP
D
)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Truth Table for Read/Write
[5]
Function (CY7C1387C)
GW
H
H
H
H
H
L
BWE
H
L
L
L
L
X
BW
B
X
H
H
L
L
X
BW
A
X
H
L
H
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write All Bytes
Write All Bytes
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE CLK
DQ
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