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參數(shù)資料
| 型號(hào)： | CY7C1386C-167BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 3.4 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CY7C1386C-167BZI |
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CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 9 of 34
CE
3 [2]
92
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW
. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device. Not connected for
BGA. Where referenced, CE
3[2]
is assumed active
throughout this document for BGA.
OE
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active LOW
.
Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are tri-stated, and act as input data pins. OE is
masked during the first clock of a read cycle when
emerging from a deselected state.
ADV
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the rising edge of
CLK, active LOW
. When asserted, it automatically
increments the address in a burst cycle.
ADSP
84
A4
B9
Input-
Synchronous
Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW
. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
ADSC
85
P4
A8
Input-
Synchronous
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW
. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
DQs, DQPs 58,59,62,63,
68,69,72,73,
8,9,12,13,18
,19,22,23,74
,24
P7,K7,G7,
E7,F6,H6,
L6,N6,D1,
H1,L1,N1,
E2,G2,K2,
M2,D6,P2
J10,K10,L10,
M10,D11,
E11,F11,G11
,J1,K1,L1,M1
,D2,E2,F2,
G2,C11,N1
I/O-
Synchronous
Bidirectional Data I/O lines
. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
X
are placed in a tri-state
condition.
V
DD
15,41,65,91
C4,J2,J4,
J6,R4
D4,D8,E4,E8
,F4,F8,G4,
G8,H4,H8,J4
,J8,K4,K8,L4
,L8,M4,M8
Power Supply
Power supply inputs to the core of the device
.
CY7C1387C:Pin Definitions
(continued)
Name
TQFP
BGA
(2-Chip
Enable)
fBGA
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1386C-200AC | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| CY7C1386C-200AI | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| CY7C1386C-200BGC | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| CY7C1387C-250AC | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| CY7C1387C | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1386D-167AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-167AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-200AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-200AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-200BGCT | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 3NS 119BGA - Tape and Reel |
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