參數(shù)資料
型號: CY7C1386C-167AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
中文描述: 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 12/34頁
文件大?。?/td> 554K
代理商: CY7C1386C-167AC
CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 12 of 34
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
00
01
10
11
Linear Burst Address Table
(MODE = GND)
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
60
2t
CYC
Unit
mA
ns
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
2t
CYC
2t
CYC
0
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE
1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
CE
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
OE CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
DQ
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
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CY7C1386C 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-225BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
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