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參數(shù)資料
| 型號(hào)： | CY7C1383F-133BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 6.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 975K |
| 代理商： | CY7C1383F-133BGXC |
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18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Cypress Semiconductor Corporation
Document #: 38-05544 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised Feburary 07, 2007
Features
Supports 133 MHz bus operations
512K × 36 and 1M × 18 common IO
3.3V core power supply (V
DD
)
2.5V or 3.3V IO supply (V
DDQ
)
Fast clock-to-output time
— 6.5 ns (133 MHz version)
Provides high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1381D/CY7C1383D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1381F/CY7C1383F available in
Pb-free and non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
Functional Description
[1]
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a
3.3V, 512K x 36 and 1M x 18 synchronous flow through
SRAMs,
designed
to
interface
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address pipelining chip enable (CE
1
), depth-expansion chip
enables (CE
2
and CE
3 [2]
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
x
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE)
and the ZZ pin.
with
high-speed
The
allows interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
The
operates from a +3.3V core power supply while all outputs
operate with a +2.5V or +3.3V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
Selection Guide
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3,
CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
[+] Feedback
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