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參數(shù)資料
| 型號(hào)： | CY7C1382FV25-167BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 3.4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 898K |
| 代理商： | CY7C1382FV25-167BGXI |
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18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Cypress Semiconductor Corporation
Document #: 38-05546 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised Feburary 15, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
2.5V core power supply
Fast clock-to-output times, 2.6 ns (for 250-MHz device)
Provides high-performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single Cycle Chip Deselect
CY7C1380DV25/CY7C1382DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1380FV25/CY7C1382FV25 available in Pb-free and
non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
Functional Description
[1]
The
CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
1
), depth expansion chip enables (CE
2
and
CE
3 [2]
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
X
, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the
ZZ pin.
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see
Pin Definitions on page 6
and
Truth Table
[4,
5, 6, 7, 8]
on page 9
for further details). Write cycles can be one
to two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 operates from a +2.5V core power supply
while all outputs may operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3
, CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1382FV25-200BGC | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1382FV25-200BGI | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1382FV25-200BGXC | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1382FV25-200BGXI | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1382FV25-250BGC | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY7C1382KV33-167AXC | 功能描述:IC SRAM 18MBIT 167MHZ 100TQFP 制造商:cypress semiconductor corp 系列:- 包裝:托盤 零件狀態(tài):在售 存儲(chǔ)器類型:易失 存儲(chǔ)器格式:SRAM 技術(shù):SRAM - 同步 存儲(chǔ)容量:18Mb （1M x 18） 時(shí)鐘頻率:167MHz 寫周期時(shí)間 - 字，頁:- 訪問時(shí)間:3.4ns 存儲(chǔ)器接口:并聯(lián) 電壓 - 電源:3.135 V ~ 3.6 V 工作溫度:0°C ~ 70°C（TA） 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商器件封裝:100-TQFP（14x20） 標(biāo)準(zhǔn)包裝:72 |
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