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參數(shù)資料
| 型號： | CY7C1382D-200BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 3 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.4 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大小： | 967K |
| 代理商： | CY7C1382D-200BZI |
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18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised Feburary 07, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V or 3.3V IO power supply
Fast clock-to-output times
— 2.6 ns (for 250 MHz device)
Provides high-performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Single cycle chip deselect
CY7C1380D/CY7C1382D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1380F/CY7C1382F available in
Pb-free and non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
Functional Description
[1]
The
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM
cells with advanced synchronous peripheral circuitry and a
two-bit counter for internal burst operation. All synchronous
inputs are gated by registers controlled by a positive edge
triggered clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining chip enable
(CE
1
), depth-expansion chip enables (CE
2
and CE
3 [2]
), burst
control inputs (ADSC, ADSP, and ADV), write enables (BW
X
,
and BWE), and global write (GW). Asynchronous inputs
include the output enable (OE) and the ZZ pin.
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as they are controlled
by the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see
Pin Definitions on page 6
and
Truth Table
[4,
5, 6, 7, 8]
on page 9
for further details). Write cycles can be one
to two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Selection Guide
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3,
CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
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