參數(shù)資料
型號(hào)： CY7C1372D-167BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
中文描述： 1M X 18 ZBT SRAM, 3.4 ns, PBGA165
封裝： (13 X 15 X 1.4) MM, PLASTIC, FBGA-165
文件頁(yè)數(shù)： 15/30頁(yè)
文件大小： 344K
代理商： CY7C1372D-167BZC
PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 15 of 30
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
[12]
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1370D
000
01011001000100101
00000110100
1
CY7C1372D
000
01011001000010101 Reserved for future use.
00000110100
Allows unique identification of SRAM vendor.
1
Indicate the presence of an ID register.
Description
Reserved for version number.
Scan Register Sizes
Register Name
Bit Size (x18)
3
1
32
85
89
Bit Size (x36)
3
1
32
85
89
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Note:
12.Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
相關(guān)PDF資料
PDF描述
CY7C1372D-167BZI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200AXC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200AXI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BGC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BGI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1372D-200AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1372D-200AXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1372D-200AXCT 功能描述:IC SRAM 18MBIT 200MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1372DV25-167AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1372DV25-167AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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