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參數(shù)資料
| 型號： | CY7C1372C-250AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 1M X 18 ZBT SRAM, 2.6 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 704K |
| 代理商： | CY7C1372C-250AC |
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CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 18 of 27
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +4.6V
DC to Outputs in Tri-State................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C 3.3V–5%/+10% 2.5V –5% to
–40°C to +85°C
V
DD
V
DDQ
V
DD
Electrical Characteristics
Over the Operating Range
[14, 15]
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
2.625
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DD
= Min., I
OH
=
4.0 mA, V
DDQ
= 3.3V
V
DD
= Min., I
OH
=
1.0 mA, V
DDQ
= 2.5V
V
DD
= Min., I
OL
=
8
.0 mA, V
DDQ
= 3.3V
V
DD
= Min., I
OL
=
1.0 mA, V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
–30
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
30
5
350
325
300
275
120
110
100
90
70
V
IL
Input LOW Voltage
[14]
I
X
Input Load Current
Input Current of MODE
Output Leakage Current GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
I
OZ
I
DD
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX
=
1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = f
MAX
= 1/t
CYC
I
SB3
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
105
100
95
85
80
mA
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
Shaded areas contain advance information.
Notes:
14.Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC)> -2V (Pulse width less than t
CYC
/2).
15.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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