參數(shù)資料
型號: CY7C1371BV25-83BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù): 1/25頁
文件大小: 709K
代理商: CY7C1371BV25-83BGC
512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
CY7C1373BV25
CY7C1371BV25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05250 Rev. *A
Revised January 18, 2003
Features
Pin-compatible and functionally equivalent to ZBT
devices
Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Registered inputs for Flow-Thru operation
Byte Write capability
Common I/O architecture
Single 2.5V +5% power supply
Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10 ns (for 83-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100-pin TQFP and 119-ball BGA packages
Burst Capability–linear or interleaved burst order
JTAG boundary scan for BGA packaging version
Automatic power-down available using ZZ mode or CE
deselect
Functional Description
The CY7C1371BV25 and CY7C1373BV25 are 2.5V, 512K×36
and 1M×18 Synchronous Flow-Thru Burst SRAMs, respec-
tively,
designed
specifically
to
support
unlimited
true
back-to-back Read/Write operations without the insertion of
wait
states.
The
CY7C1371BV25/CY7C1373BV25
is
equipped with the advanced No Bus Latency (NoBL
) logic
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write/Read
transitions.The
CY7C1371BV25/CY7C1373BV25
is
pin-
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the Byte Write Selects
(BWSa,b,c,d
for
CY7C1371BV25
and
BWSa,b
for
CY7C1373BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
ZZ may be tied to LOW if it is not used.
Synchronous Chip Enable (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output Enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a write
sequence.
Selection Guide
117 MHz
100 MHz
83 MHz
Unit
Maximum Access Time
7.5
8.5
10.0
ns
Maximum Operating Current
210
190
160
mA
Maximum CMOS Standby Current
30
mA
CLK
Ax
CEN
WE
BWSx
CE1
CE
CE2
OE
256KX36/
MEMORY
ARRAY
Logic Block Diagram
DQx
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
Mode
DPx
CY7C1371
CY7C1373
AX
DQX
DPX
BWSX
512KX18
X = 18:0
X = 19:0
X= a, b, c, d X = a, b
X = a, b
X = a, b, c, d
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