參數(shù)資料
型號: CY7C1364B
廠商: Cypress Semiconductor Corp.
英文描述: 9-Mb (256K x 32) Pipelined Sync SRAM(9-Mb (256K x 32)管道式同步SRAM)
中文描述: 9紅蛋白(256K × 32)流水線同步靜態(tài)存儲器(9字節(jié)(256K × 32)管道式同步靜態(tài)存儲器)
文件頁數(shù): 1/16頁
文件大小: 334K
代理商: CY7C1364B
9-Mb (256K x 32) Pipelined Sync SRAM
CY7C1364B
Cypress Semiconductor Corporation
Document #: 38-05420 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 26, 2004
Features
Registered inputs and outputs for pipelined operation
256K × 32 common I/O architecture
3.3V core power supply
3.3V I/O operation
Fast clock-to-output times
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP package
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1364B SRAM integrates 262,144 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1364B operates from a +3.3V core power supply
while all outputs also operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
ARRAY
DQs
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
D
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE DRIVER
DQ
B
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
DQ
D
BYTE
WRITE DRIVER
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