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參數(shù)資料
| 型號： | CY7C1361B |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 中文描述： | 9兆位（256 × 36/512K × 18）流通過的SRAM |
| 文件頁數(shù)： | 1/34頁 |
| 文件大?。?/td> | 862K |
| 代理商： | CY7C1361B |
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9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM
CY7C1361B
CY7C1363B
Cypress Semiconductor Corporation
Document #: 38-05302 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 20, 2004
Features
Supports 133-MHz bus operations
256K X 36/512K X 18 common I/O
3.3V –5% and +10% core power supply (V
DD
)
2.5V or 3.3V I/O supply (V
DDQ
)
Fast clock-to-output times
—6.5 ns (133-MHz version)
—7.5 ns (117-MHz version)
—8.5 ns (100-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-ball fBGA packages
— Both 2 and 3 Chip Enable Options for TQFP
JTAG boundary scan for BGA and fBGA packages
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K
x 18 Synchronous Flow through SRAMs, respectively
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
3[2]
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1361B/CY7C1363B allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1361B/CY7C1363B operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
250
30
117 MHz
7.5
220
30
100 MHz
8.5
180
30
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is for A version of TQFP (3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1361B-117AI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| CY7C1363B-117AC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| CY7C1362A-150BGI | 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM |
| CY7C1362A-166AC | 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM |
| CY7C1362A-166AI | 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1361B-100AC | 功能描述:IC SRAM 9MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1361B-100AJC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 8.5ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1361B-100BGC | 功能描述:IC SRAM 9MBIT 100MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1361B-100BGCT | 制造商:Rochester Electronics LLC 功能描述:256KX36 3.3V SYNC-FT SRAM - Tape and Reel |
| CY7C1361B-100BZI | 制造商:Rochester Electronics LLC 功能描述:256KX36 3.3V SYNC-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
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