參數(shù)資料
型號： CY7C1360B-166AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： CONNECTOR ACCESSORY
中文描述： 256K X 36 CACHE SRAM, 3.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù)： 9/34頁
文件大小： 895K
代理商： CY7C1360B-166AC
CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 9 of 34
CY7C1362B–Pin Definitions
Name
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
BGA
fBGA
I/O
Description
A
0
, A
1
, A
37,36,32,
33,34,35,
43,44,45,
46,47,48,
49,50,80,
81,82,99,
100
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,80,81,
82,92,99,
100
P4,N4,
A2,C2,
R2,T2,
A3,B3,
C3,T3,
A5,B5,
C5,T5,
A6,B6,
C6,R6,
T6
R6,P6,A2,
A10,A11,
B2,B10,P3,
P4,P8,P9,
P10,P11,
R3,R4,R8,
R9,R10,
R11
Input-
Synchronous
Address Inputs used to select one of the 512K
address locations
. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3[2]
are sampled active. A
1
, A
0
are fed
to the two-bit counter..
BW
A,
BW
B
93,94
93,94
G3,L5
B5,A4
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified
with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
GW
88
88
H4
B7
Input-
Synchronous
Global Write Enable Input, active LOW
. When
asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BW
X
and BWE).
BWE
87
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW
. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
CLK
89
89
K4
B6
Input-
Clock
Clock Input
. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during
a burst operation.
CE
1
98
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
2
and CE
3[2]
to select/deselect the device.
ADSP is ignored if CE
1
is HIGH.
CE
2
97
97
B2
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
1
and CE
3[2]
to select/deselect the device.
CE
3 [2]
92
-
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device. Not
available for AJ package version. Not connected
for BGA. Where referenced, CE
3[2]
is assumed
active throughout this document for BGA.
OE
86
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active
LOW
. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and
act as input data pins. OE is masked during the first
clock of a Read cycle when emerging from a
deselected state.
ADV
83
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the rising
edge of CLK, active LOW
. When asserted, it
automatically increments the address in a burst
cycle.
相關(guān)PDF資料
PDF描述
CY7C1360B-166AI CONNECTOR ACCESSORY
CY7C1360B-166AJC CONNECTOR ACCESSORY
CY7C1360B-166AJI CONNECTOR ACCESSORY
CY7C1360B-166BGC CONNECTOR ACCESSORY
CY7C1360B-166BGI CONNECTOR ACCESSORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1360B-166AJC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 9MBIT 256KX36 3.5NS 100TQFP - Bulk
CY7C1360B-166AJI 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述:
CY7C1360B-166BGC 功能描述:IC SRAM 9MBIT 166MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤
CY7C1360B-200AC 制造商:Cypress Semiconductor 功能描述:
CY7C1360B-200AJC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 9MBIT 256KX36 3NS 100TQFP - Bulk
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