參數(shù)資料
型號(hào)： CY7C1357V25
廠商： Cypress Semiconductor Corp.
英文描述： 512Kx18 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的512Kx18流通式 靜態(tài)RAM)
中文描述： 512Kx18流過(guò)式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的512Kx18流通式靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/26頁(yè)
文件大?。?/td> 335K
代理商： CY7C1357V25
PRELIMINARY
256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture
CY7C1355V25
CY7C1357V25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
December 2, 1999
408-943-2600
5
Features
Pin compatible and functionally equivalent to ZBT
devices
Supports 133-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Registered inputs for Flow-Through operation
Byte Write capability
Common I/O architecture
Single 2.5V power supply
Fast clock-to-output times
—6.5 ns (for 133-MHz device)
—7.5 ns (for 117-MHz device)
—8.5 ns (for 100-MHz device)
—10.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability—linear or interleaved burst order
Functional Description
The CY7C1355V25 and CY7C1357V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Flow-Through Burst SRAMs,
respectively. They are designed specifically to support unlim-
ited true back-to-back Read/Write operations without the in-
sertion of wait states. The CY7C1355V25/CY7C1357V25 is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature dra-
matically improves the throughput of data through the SRAM,
especially in systems that require frequent Write/Read transi-
tions. The CY7C1355V25/CY7C1357V25 is pin compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 6.5 ns (133-MHz de-
vice).
Write operations are controlled by the Byte Write Selects
(BWS
a,b,c,d
for
CY7C1355V25
CY7C1357V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
and
BWS
a,b
for
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology.
CLK
A
x
CEN
CE1
CE2
WE
BWS
x
Mode
CE
OE
256KX36/
512KX18
MEMORY
ARRAY
Logic Block Diagram
DQ
x
DP
x
DaD
Q
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
CY7C1355
X = 17:0
X= a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1357
X = 18:0
X = a, b
X = a, b
X = a, b
A
X
DQ
X
DP
X
BWS
X
Selection Guide
7C1355V25-133
7C1357V25-133
7C1355V25-117
7C1357V25-117
7C1355V25-100
7C1357V25-100
7C1355V25-80
7C1357V25-80
Maximum Access Time (ns)
6.5
7.5
8.5
10.0
Maximum Operating Current (mA)
Com’l
300
280
250
200
Maximum CMOS Standby Current (mA) Com’l
10
10
10
10
Shaded areas contain advance information.
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