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參數(shù)資料
| 型號： | CY7C1357C-133BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| 中文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 456K |
| 代理商： | CY7C1357C-133BZXI |
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CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. *E
Page 15 of 28
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
69
69
Bit Size (x18)
3
1
32
69
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1355C-100BGXI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C-100BZXC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C-100BZXI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C-133AXC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C-133AXI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1357S-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1357S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1357S-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1357S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1359A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Cypress Semiconductor 功能描述:256K X 18 CACHE TAG SRAM, 4 ns, PQFP100 |
| CY7C1359A-100ACT | 制造商:Cypress Semiconductor 功能描述: 制造商:Cypress Semiconductor 功能描述:Electronic Component |
| CY7C1359A-150AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 256K x 16 3.8ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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