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參數(shù)資料
| 型號： | CY7C1356CV25-225BGI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構(gòu) |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 353K |
| 代理商： | CY7C1356CV25-225BGI |
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 8 of 25
deasserted HIGH before presenting data to the DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for CY7C1356CV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
and DQP
(DQ
a,b,c,d
/
DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for
CY7C1356CV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354CV25/56CV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE
1
, CE
2
, and CE
3
) and
WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
a,b,c,d
for CY7C1354CV25 and BW
a,b
for
CY7C1356CV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
ZZ Mode Electrical Characteristics
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3,
must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
Address
A1,A0
A1,A0
00
01
01
00
10
11
11
10
Second
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Description
Test Conditions
Min.
Max
50
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
ZZ
>
V
DD
0.2V
ZZ
>
V
DD
0.2V
ZZ
<
0.2V
This parameter is sampled
This parameter is sampled
2t
CYC
2t
CYC
0
Operation
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
X
OE
CEN
L
L
L
L
L
L
L
L
L
L
H
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
DQ
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Notes:
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BW
. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
X
= Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.
X
X
L
L
H
H
X
X
X
X
X
X
Three-State
Three-State
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
–
Three-State
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