參數(shù)資料
型號: CY7C1356CV25-166BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
中文描述: 512K X 18 ZBT SRAM, 3.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 13/28頁
文件大?。?/td> 444K
代理商: CY7C1356CV25-166BZI
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *H
Page 13 of 28
2.5V TAP AC Test Conditions
Input pulse levels ............................................... V
SS
to 2.5V
Input rise and fall time .................................................... 1 ns
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)
[13]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Identification Register Definitions
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
Min.
2.0
2.1
Max.
Unit
V
V
V
V
V
V
μA
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA,V
DDQ
= 2.5V
I
OL
= 8.0 mA, V
DDQ
= 2.5V
I
OL
= 100 μA
0.4
0.2
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
1.7
–0.3
–5
V
DD
+ 0.3
0.7
5
GND < V
IN
< V
DDQ
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Scan Register Sizes
CY7C1354CV25
000
01011001000100110
00000110100
1
CY7C1356CV25
000
01011001000010110 Reserved for future use.
00000110100
Allows unique identification of SRAM vendor.
1
Indicate the presence of an ID register.
Description
Reserved for version number.
Register Name
Bit Size (x36)
3
1
32
69
Bit Size (x18)
3
1
32
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA
package)
Boundary Scan Order (165-ball FBGA
package)
Identification Codes
69
69
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Note:
13.All voltages referenced to V
SS
(GND).
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相關(guān)PDF資料
PDF描述
CY7C1356CV25-166BZXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356CV25-166BZXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
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CY7C1356CV25-200AXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1356CV25-166CKJ 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1356CV25-200AXC 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx18 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1356CV25-200AXCT 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx18 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1356CV25-250AXC 制造商:Rochester Electronics LLC 功能描述:- Bulk
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