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參數(shù)資料
| 型號： | CY7C1355C-133BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 256K X 36 ZBT SRAM, 6.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 496K |
| 代理商： | CY7C1355C-133BZC |
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PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 18 of 33
Identification Register Definitions
Instruction Field
CY7C1355C
(256Kx36)
CY7C1357C
(512Kx18)
Description
Revision Number (31:29)
010
010
Describes the version number
Device Depth (28:24)
01010
01010
Reserved for Internal Use
Device Width (23:18)
001001
001001
Defines memory type and architecture
Cypress Device ID (17:12)
100110
010110
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM vendor
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball fBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1355C-133BZI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1357C-100AI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1357C-117AC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1357C-117AI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1357C-117BGC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1355S-133AXC | 功能描述:IC SRAM 256KX36 3.3V SYN 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1355S-133AXCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1355S-133BGC | 功能描述:IC SRAM 256KX36 NOBL 119-BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1356-166AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1356A-100AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 512K x 18 5ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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