參數(shù)資料
型號: CY7C1355C-133AI
廠商: Cypress Semiconductor Corp.
英文描述: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
中文描述: 9兆位(256 × 36/512K × 18)流體系結(jié)構(gòu),通過與總線延遲靜態(tài)存儲器
文件頁數(shù): 10/32頁
文件大小: 496K
代理商: CY7C1355C-133AI
PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 10 of 33
.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
.
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
35
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
相關(guān)PDF資料
PDF描述
CY7C1355C-133BGC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BGI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BZC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BZI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-100AI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
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