參數(shù)資料
型號： CY7C1355C-133AC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
中文描述： 9兆位（256 × 36/512K × 18）流體系結構，通過與總線延遲靜態(tài)存儲器
文件頁數(shù)： 25/32頁
文件大?。?/td> 496K
代理商： CY7C1355C-133AC
PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 25 of 33
Switching Characteristics
Over the Operating Range
[20, 21, 22, 23, 24, 25]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Notes:
20.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a Read or Write operation
can be initiated.
23.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
24.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
25.This parameter is sampled and not 100% tested.
Description
133 MHz
Min.
1
117 MHz
Min.
1
100 MHz
Min.
1
Unit
ms
Max.
Max.
Max.
V
DD
(Typical) to the First Access
[22]
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
3.0
3.0
8.5
3.2
3.2
10
4.0
4.0
ns
ns
ns
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z
[23, 24, 25]
Clock to High-Z
[23, 24, 25]
OE LOW to Output Valid
OE LOW to Output Low-Z
[23, 24, 25]
OE HIGH to Output High-Z
[23, 24, 25]
6.5
7.0
7.5
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
2.0
0
3.5
3.5
3.5
3.5
3.5
3.5
0
0
0
3.5
3.5
3.5
Address Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ADV/LD Set-up before CLK Rise
WE, BW
X
Set-up before CLK Rise
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Address Hold after CLK Rise
ADV/LD Hold after CLK Rise
WE, BW
X
Hold after CLK Rise
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
相關PDF資料
PDF描述
CY7C1355C-133AI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BGC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BGI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BZC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133BZI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
相關代理商/技術參數(shù)
參數(shù)描述
CY7C1355C-133AXC 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1355C-133AXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1355C-133AXCT 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1355C-133AXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1355C-133AXIT 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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