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參數(shù)資料
| 型號： | CY7C1355B-100BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 256K X 36 ZBT SRAM, 7.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 1/33頁 |
| 文件大小： | 560K |
| 代理商： | CY7C1355B-100BZC |
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9-Mb (256K x 36/512K x 18) Flow-Through
SRAM with NoBL Architecture
CY7C1355B
CY7C1357B
Cypress Semiconductor Corporation
Document #: 38-05117 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 27, 2004
Features
No Bus Latency (NoBL) architecture eliminates
dead cycles between write and read cycles.
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
3.3V/2.5V I/O power supply
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.0 ns (for 117-MHz device)
— 7.5 ns (for 100-MHz device)
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Asynchronous Output Enable
Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
Three chip enables for simple depth expansion.
Automatic Power-down feature available using ZZ
mode or CE deselect.
JTAG boundary scan for BGA and fBGA packages
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
the
insertion
CY7C1355B/CY7C1357B is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
of
wait
states.
The
Selection Guide
133 MHz
6.5
250
30
117 MHz
7.0
220
30
100 MHz
7.5
180
30
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1355B-100BZI | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355B-117AC | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355B-117AI | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355B-117BGC | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355B-117BGI | 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1355B-117AC | 功能描述:IC SRAM 9MBIT 117MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1355B-117AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 9M-Bit 256K x 36 7ns 100-Pin TQFP |
| CY7C1355B-117BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 9M-Bit 256K x 36 7ns 119-Pin BGA 制造商:Cypress Semiconductor 功能描述:256K X 36 ZBT SRAM, 7 ns, PBGA119 |
| CY7C1355B-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 6.5ns 100-Pin TQFP |
| CY7C1355C-100AXC | 功能描述:IC SRAM 9MBIT 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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