參數(shù)資料
型號： CY7C1354V25
廠商： Cypress Semiconductor Corp.
英文描述： 256Kx36 Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的256Kx36流水線式 SRAM)
中文描述： 256Kx36流水線與總線延遲靜態(tài)存儲器體系結(jié)構(gòu)（帶總線延遲結(jié)構(gòu)的256Kx36流水線式的SRAM）
文件頁數(shù)： 1/26頁
文件大?。?/td> 340K
代理商： CY7C1354V25
PRELIMINARY
256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture
Features
CY7C1354V25
CY7C1356V25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
December 2, 1999
408-943-2600
5
Pin compatible and functionally equivalent to ZBT
Supports 200-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully Registered (inputs and outputs) for pipelined op-
eration
Byte Write capability
Common I/O architecture
Single 2.5V power supply
Fast clock-to-output times
—3.2 ns (for 200-MHz device)
—3.5 ns (for 166-MHz device)
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability—linear or interleaved burst order
Functional Description
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-
spectively. They are designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The CY7C1354V25/CY7C1356V25 is equipped
with the advanced No Bus Latency (NoBL) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions. The
CY7C1354V25/CY7C1356V25 is pin compatible and function-
ally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.2 ns (200-MHz device).
Write operations are controlled by the Byte Write Selects
(BWS
a
–BWS
d
for CY7C1354V25 and BWS
a
–BWS
b
for
CY7C1356V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
CLK
A
x
CEN
CE
1
CE
2
WE
BWS
x
Mode
CE
OE
256KX36/
512KX18
MEMORY
ARRAY
Logic Block Diagram
DQ
x
DP
x
DaD
Q
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
CY7C1354
X = 17:0
CY7C1356
X = 18:0
X = a, b, c, d
A
X
DQ
X
DP
X
BWS
X
X = a, b
X = a, b
X = a, b
X = a, b, c, d
X = a, b, c, d
O
R
a
Selection Guide
7C1354V25-200
7C1356V25-200
7C1354V25-166
7C1356V25-166
7C1354V25-133
7C1356V25-133
7C1354V25-100
7C1356V25-100
Maximum Access Time (ns)
3.2
3.5
4.0
5.0
Maximum Operating Current (mA)
Com’l
475
450
370
300
Maximum CMOS Standby Current (mA) Com’l
10
10
10
10
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
相關(guān)PDF資料
PDF描述
CY7C1356V25 512Kx18 Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的512Kx18流水線式 SRAM)
CY7C1355B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-133BZC 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-133BZI 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
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