- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379063 > CY7C1354CV25-200BZXI (CYPRESS SEMICONDUCTOR CORP) 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1354CV25-200BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 256K X 36 ZBT SRAM, 3.2 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 444K |
| 代理商： | CY7C1354CV25-200BZXI |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL Architecture
CY7C1354CV25
CY7C1356CV25
Cypress Semiconductor Corporation
Document #: 38-05537 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 14, 2006
Features
Pin-compatible with and functionally equivalent to
ZBT
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 166 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
Single 2.5V power supply (V
DD
)
Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability
–
linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
[1]
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency (NoBL
)
logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for
CY7C1354CV25
CY7C1356CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
and
BW
a
–BW
b
for
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A0, A1, A
C
MODE
BW
a
BW
b
BW
c
BW
d
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram–CY7C1354CV25 (256K x 36)
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1356CV25 | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1356CV25-166AXC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1356CV25-166AXI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1355C-100BGXC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1354CV25-200CKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1354D-200BZC | 制造商:Cypress Semiconductor 功能描述:SYNC SRAMS - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 9MBIT 200MHZ 165FBGA |
| CY7C1354DV25-200BZI | 功能描述:靜態(tài)隨機存取存儲器 256Kbx36 2.4V-2.6V 9Mb 200MHz PIPELINE RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1354S-166AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1354S-166AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1354S-166BGC | 功能描述:IC SRAM 256KX36 3.3V SYNC 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。