參數(shù)資料
型號(hào)： CY7C1354CV25-167AXC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
中文描述： 9兆位（256 × 36/512K × 18）流水線(xiàn)的SRAM的總線(xiàn)延遲，TM架構(gòu)
文件頁(yè)數(shù)： 1/25頁(yè)
文件大小： 353K
代理商： CY7C1354CV25-167AXC
PRELIMINARY
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
with NoBL Architecture
CY7C1354CV25
CY7C1356CV25
Cypress Semiconductor Corporation
Document #: 38-05537 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 1, 2004
Features
Pin-compatible with and functionally equivalent to
ZBT
Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 167 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
Single 2.5V power supply
Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 167-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA
packages
IEEE 1149.1 JTAG Boundary Scan
Burst capability
–
linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency (NoBL
)
logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for
CY7C1354CV25
CY7C1356CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
and
BW
a
–BW
b
for
A0, A1, A
C
MODE
BW
a
BW
b
BW
c
BW
d
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram–CY7C1354CV25 (256K x 36)
相關(guān)PDF資料
PDF描述
CY7C1356CV25-225AXC 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225AXI 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BGC 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BGI 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BGXC 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1354CV25-200AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 2.5V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1354CV25-200AXCT 功能描述:IC SRAM 9MBIT 200MHZ 100LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2
CY7C1354CV25-200BZC 制造商:Cypress Semiconductor 功能描述:CY7C1354CV25 9 Mb (256 K x 36) 200 MHz 2.5 V Pipelined SRAM - BGA-165 制造商:Cypress Semiconductor 功能描述:CY7C1354CV25 9 Mb (256 K x 36) 200 MHz 2.5 V Pipelined SRAM - FBGA-165
CY7C1354CV25-200CKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1354D-200BZC 制造商:Cypress Semiconductor 功能描述:SYNC SRAMS - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 9MBIT 200MHZ 165FBGA
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