參數(shù)資料
型號(hào): CY7C1354C-200BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
中文描述: 256K X 36 ZBT SRAM, 3.2 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁(yè)數(shù): 28/28頁(yè)
文件大?。?/td> 467K
代理商: CY7C1354C-200BGC
CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 28 of 28
Document History Page
Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
Document Number: 38-05538
Orig. of
Change
**
242032
See ECN
RKF
New data sheet
*A
278130
See ECN
RKF
Changed Boundary Scan order to match the B Rev of these devices
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
*B
284431
See ECN
VBL
Changed ISB1 and ISB3 from DC Characteristic table as follows
ISB1: 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Add BG and BZ pkg lead-free part numbers to ordering info section
*C
320834
See ECN
PCI
Changed 225 MHz to 250 MHz
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection
Guide
Changed
Θ
JA
and
Θ
JC
for TQFP Package
from 25 and 9
°
C/W to 29.41 and
6.13
°
C/W respectively
Changed
Θ
JA
and
Θ
JC
for BGA Package
from 25 and 6
°
C/W to 34.1 and
14.0
°
C/W respectively
Changed
Θ
JA
and
Θ
JC
for FBGA Package
from 27 and 6
°
C/W to 16.8 and
3.0
°
C/W respectively
Modified V
OL,
V
OH
test conditions
Added Lead-Free product information
Updated Ordering Information Table
Changed from Preliminary to Final
*D
351895
See ECN
PCI
Changed I
SB2
from 35 to 40 mA
Updated Ordering Information Table
*E
377095
See ECN
PCI
Modified test condition in note# 15 from V
DDQ
< V
DD
to
V
DDQ
V
DD
*F
408298
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
*G
501793
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
REV.
ECN No.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1354C-200BGI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BZC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356C-166BZXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
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