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參數(shù)資料
| 型號(hào)： | CY7C1353G-117AXI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 18) Flow-through SRAM with NoBL⑩ Architecture |
| 中文描述： | 4兆位（256 × 18）流通過(guò)總線延遲⑩建筑的SRAM |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | CY7C1353G-117AXI |
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PRELIMINARY
4-Mbit (256K x 18) Flow-through SRAM
with NoBL Architecture
CY7C1353G
Cypress Semiconductor Corporation
Document #: 38-05515 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised October 22, 2004
Features
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
256K x 18 common I/O architecture
2.5V / 3.3V I/O power supply
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.0 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
Pb-Free 100 TQFP package
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency (NoBL) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1.For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
ZZ
OE
READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
SLEEP
CONTROL
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1354A-100ACI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-100BGCI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-133ACI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-133BGCI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-166ACI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1353G-133AXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1353S-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1353S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1353S-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1353S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1354 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1354A-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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