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參數(shù)資料
| 型號： | CY7C1352G_06 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 18) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 4兆位（256 × 18）的總線延遲⑩架構(gòu)流水線的SRAM |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 309K |
| 代理商： | CY7C1352G_06 |
4-Mbit (256K x 18) Pipelined SRAM with
NoBL Architecture
CY7C1352G
Cypress Semiconductor Corporation
Document #: 38-05514 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 4, 2006
Features
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Byte Write capability
256K x 18 common I/O architecture
3.3V core power supply (V
DD
)
2.5V/3.3V I/O power supply (V
DDQ
)
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Available in lead-free 100-Pin TQFP package
Burst Capability—linear or interleaved burst order
ZZ” Sleep Mode Option and Stop Clock option
Functional Description
[1]
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352G is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A0, A1, A
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
A
DQP
B
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
CSleep
Logic Block Diagram
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1352G-166AXC | 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture |
| CY7C1352G-166AXI | 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture |
| CY7C1352G-200AXC | 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture |
| CY7C1352G-200AXI | 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture |
| CY7C1352G-250AXC | 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture |
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|---|---|
| CY7C1352G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1352G-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1352G-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1352G-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1352G-133AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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