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參數(shù)資料
| 型號： | CY7C1351G-133BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 6.5 ns, PBGA119 |
| 封裝： | 22 X 14 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 373K |
| 代理商： | CY7C1351G-133BGC |
4-Mbit (128K x 36) Flow-through SRAM
with NoBL Architecture
CY7C1351G
Cypress Semiconductor Corporation
Document #: 38-05513 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 4, 2006
Features
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
128K x 36 common I/O architecture
2.5V/3.3V I/O power supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1351G is a 3.3V, 128K x 36 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351G is equipped with the
advanced No Bus Latency (NoBL) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the four Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
MEMORY
ARRAY
E
INPUT
REGISTER
BW
C
BW
D
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
Control
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1351GC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1351S-100AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1351S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1351S-100AXCT | 功能描述:靜態(tài)隨機存取存儲器 CY7C1351S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1351S-133AXC | 功能描述:IC SRAM 128KX36 SYNC 100-TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C135-20JCT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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