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參數(shù)資料
| 型號： | CY7C1347G-250BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| 中文描述： | 128K X 36 CACHE SRAM, 2.6 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 841K |
| 代理商： | CY7C1347G-250BGC |
CY7C1347G
Document #: 38-05516 Rev. *E
Page 10 of 21
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life
of the device. User guidelines are not tested.
Storage Temperature
.....................................
65
°
C to +150
°
C
Ambient Temperature with
Power Applied
..................................................
55
°
C to +125
°
C
Supply Voltage on V
DD
Relative to GND
.........
0.5V to +4.6V
Supply Voltage on V
DDQ
Relative to GND
.......
0.5V to +V
DD
DC Voltage Applied to Outputs
in High-Z State
...........................................
0.5V to V
DD
+ 0.5V
DC Input Voltage
.......................................
0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
Commercial
Industrial
3.3V
5%/+10%
2.5V
5%
to V
DD
Electrical Characteristics
Over the Operating Range
[8, 9]
Parameter
V
DD
V
DDQ
V
OH
Description
Test Conditions
Min
3.135
2.375
2.4
2.0
Max
3.6
V
DD
Unit
V
V
V
V
V
V
V
V
V
V
μ
A
Power Supply Voltage
IO Supply Voltage
Output HIGH Voltage
For 3.3V IO, I
OH
= –4.0 mA
For 2.5V IO, I
OH
= –1.0 mA
For 3.3V IO, I
OL
= 8.0 mA
For 2.5V IO, I
OL
= 1.0 mA
For 3.3V IO
For 2.5V IO
For 3.3V IO
For 2.5V IO
GND < V
I
< V
DDQ
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
[8]
2.0
1.7
–0.3
–0.3
5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
Input LOW Voltage
[8]
I
X
Input Leakage Current
Except ZZ and MODE
Input Current of MODE
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
Input Current of ZZ
5
30
5
325
265
240
225
120
110
100
90
40
I
OZ
I
DD
Output Leakage Current
V
DD
Operating Supply
Current
5
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
All speeds
I
SB1
Automatic CE
Power Down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
> V
IH
or V
IN
< V
IL
f = f
MAX
= 1/t
CYC
I
SB2
Automatic CE
Power Down
Current—CMOS Inputs
Max. V
DD
, Device Deselected,
V
IN
< 0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
Notes
8. Overshoot: V
(AC) < V
+1.5V (pulse width less than t
/2). Undershoot: V
(AC) > –2V (pulse width less than t
CYC
/2).
9. T
Power-up
: assumes a linear ramp from 0V to V
DD
(min) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
[+] Feedback
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