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參數(shù)資料
| 型號： | CY7C1347C-250AC |
| 英文描述： | x36 Fast Synchronous SRAM |
| 中文描述： | x36快速同步SRAM |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CY7C1347C-250AC |
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
5
128K X 36 Pin Descriptions
X36 BGA Pins
X36 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write: A byte write is LOW for a Write cycle and HIGH for
a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock
’
s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP
6B
92
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device.
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs.
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output.
1B, 7B, 1C, 7C,
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 6U
14, 16, 66
NC
-
No Connect: These signals are not internally connected.
256K X 18 Pin Descriptions
X18 BGA Pins
X18 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46,
45, 44, 49, 50
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
3G
93
94
BWa
BWb
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a Write
cycle and HIGH for a Read cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the setup and hold times around the rising
edge of CLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1347C-250BGC | x36 Fast Synchronous SRAM |
| GVT1256DA18B-4 | x18 Fast Synchronous SRAM |
| GVT1256DA18B-4.4 | x18 Fast Synchronous SRAM |
| GVT1256DA18B-5 | x18 Fast Synchronous SRAM |
| GVT1256DA18B-6 | x18 Fast Synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1347D-166AC | 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 36) 3.3V SYNC PIPELINE SRAM 1.5/.5 NS SETUP/HOLD - Bulk |
| CY7C1347D-200AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347D-250AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347DP | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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