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參數(shù)資料
| 型號： | CY7C1340F-250AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 32) Pipelined DCD Sync SRAM |
| 中文描述： | 128K X 32 CACHE SRAM, 2.6 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 348K |
| 代理商： | CY7C1340F-250AI |
4-Mb (128K x 32) Pipelined DCD Sync SRAM
CY7C1340F
Cypress Semiconductor Corporation
Document #: 38-05219 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 19, 2004
Features
Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
128K × 32-bit common I/O architecture
3.3V –5% and +10% core power supply (V
DD
)
3.3V / 2.5V I/O supply (V
DDQ
)
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100-pin TQFP package and pinout
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1340F operates from a +3.3V core power supply
while all outputs operate with a +3.3V or a +2.5V supply. All
inputsand outputs are JEDEC-standard JESD8-5-compatible..
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Selection Guide
250 MHz
2.6
325
40
225 MHz
2.6
290
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
100 MHz
4.5
205
40
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
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| CY7C1340G-100AXC | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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