參數(shù)資料
型號: CY7C133
廠商: Cypress Semiconductor Corp.
英文描述: 2K x 16 Dual-Port Static RAM
中文描述: 2K × 16雙口靜態(tài)存儲器
文件頁數(shù): 4/13頁
文件大?。?/td> 506K
代理商: CY7C133
CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 4 of 13
Table 1. Non-Contending Read/Write Control
Control
I/O
Operation
R/W
LB
X
L
L
H
L
H
H
H
R/W
UB
X
L
H
L
H
L
H
H
CE
H
L
L
L
L
L
L
L
OE
X
X
L
L
H
H
L
H
I/O
0
–I/O
8
High Z
Data In
Data In
Data Out
Data In
High Z
Data Out
High Z
I/O
9
–I/O
17
High Z
Data In
Data Out
Data In
High Z
Data In
Data Out
High Z
Deselected: Power-Down
Write to Both Bytes
Write Lower Byte, Read Upper Byte
Read Lower Byte, Write Upper Byte
Write to Lower Byte
Write to Upper Byte
Read to Both Bytes
High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs
Outputs
Function
CE
L
X
H
X
L
CE
R
X
X
H
L
Address
L
Address
R
No Match
Match
Match
Match
BUSY
L
H
H
H
Note 3
BUSY
R
H
H
H
Note 3
Normal
Normal
Normal
Write Inhibit
[4]
32-Bit Master/Slave Dual-Port Memory Systems
Table 3. Arbitration Results
Case
1
2
3
4
5
6
7
8
Port
Winning Port
L
R
L
R
L
R
L
R
Result
Left
Read
Read
Read
Read
Write
Write
Write
Write
Right
Read
Read
Write
Write
Read
Read
Write
Write
Both ports read
Both ports read
L port reads OK R port write inhibited
R port writes OK L port data may be invalid
L port writes OK R port data may be invalid
R port reads OK L port write inhibited
L port writes OK R port write inhibited
R port writes OK L port write inhibited
Notes:
3.
4.
The loser of the port arbitration will receive BUSY = “L” (BUSY
or BUSY
= “L”). BUSY
and BUSY
cannot both be LOW simultaneously.
Writes are inhibited to the left port when BUSY
L
is LOW. Writes are inhibited to the right port when BUSY
R
is LOW.
LEFT
RIGHT
R/W
BUSY
R/W
BUSY
R/W
BUSY
BUSY
R/W
CY7C133
CY7C143
5V
5V
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