參數(shù)資料
型號: CY7C1327C-250AC
英文描述: x18 Fast Synchronous SRAM
中文描述: x18快速同步SRAM
文件頁數(shù): 7/24頁
文件大小: 293K
代理商: CY7C1327C-250AC
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
7
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
None
CE
H
CE2
X
CE2
X
ADSP
X
ADSC
L
ADV
X
WRITE
X
OE
X
CLK
L-H
DQ
High-Z
Deselected Cycle, Power Down
Deselected Cycle, Power Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
Partial Truth Table for READ/WRITE
[9]
FUNCTION
GW
BWE
BWa
BWb
BWc
BWd
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE one byte
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
Note:
2.
X means
don
t care.
H means logic HIGH. L means logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.
For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
For X18 product, there are only BWa and BWb.
3.
4.
5.
6.
7.
8.
9.
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