參數(shù)資料
型號: CY7C1257V18-333BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 4M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 7/27頁
文件大?。?/td> 1037K
代理商: CY7C1257V18-333BZI
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 7 of 27
ZQ
Input
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW
. Connecting this pin to ground turns off the DLL inside the device.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with DDR-I timing.
TDO
Output
TDO for JTAG
.
TCK
Input
TCK pin for JTAG
.
TDI
Input
TDI pin for JTAG
.
TMS
Input
TMS pin for JTAG
.
NC
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die
. Can be tied to any voltage level.
V
REF
Input-
Reference
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs, outputs,
and AC measurement points.
V
DD
Power Supply
Power supply inputs to the core of the device
.
V
SS
Ground
Ground for the device
.
V
DDQ
Power Supply
Power supply inputs for the outputs of the device
.
Pin Definitions
(continued)
Pin Name
IO
Pin Description
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1257V18-333BZXC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1257V18-333BZXI 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1257V18-375BZC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1257V18-375BZI 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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