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參數(shù)資料
| 型號(hào)： | CY7C1256V18-300BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大小： | 1042K |
| 代理商： | CY7C1256V18-300BZI |
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CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 11 of 28
Write Cycle Descriptions
The write cycle description table for CY7C1241V18 and CY7C1243V18 follows.
[2, 10]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
L
L
L–H
–
During the data portion of a write sequence
:
CY7C1241V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1243V18
both bytes (D
[17:0]
) are written into the device.
L-H During the data portion of a write sequence
:
CY7C1241V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1243V18
both bytes (D
[17:0]
) are written into the device.
During the data portion of a write sequence
:
CY7C1241V18
only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1243V18
only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L–H During the data portion of a write sequence
:
CY7C1241V18
only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1243V18
only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
During the data portion of a write sequence
:
CY7C1241V18
only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1243V18
only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
L–H During the data portion of a write sequence
:
CY7C1241V18
only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1243V18
only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
L
L
–
L
H
L–H
–
L
H
–
H
L
L–H
–
H
L
–
H
H
L–H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1256V18 follows.
[2, 10]
BWS
0
L
K
K
Comments
L–H
–
During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
No data is written into the device during this portion of a write operation.
L
–
L–H
H
L–H
–
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
10.Assumes a write cycle was initiated per the Write Cycle Description Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered in different portions of
a write cycle, as long as the setup and hold requirements are met.
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| CY7C1256V18-300BZXC | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
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