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參數(shù)資料
| 型號： | CY7C1250V18-333BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | CY7C1250V18-333BZXI |
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 27 of 27
Document History Page
Document Title: CY7C1246V18/CY7C1257V18/CY7C1248V18/CY7C1250V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Ar-
chitecture (2.0 Cycle Read Latency)
Document Number: 001-06348
Orig. of
Change
**
425689
See ECN
NXR
New Data Sheet
*A
461639
See ECN
NXR
Revised the MPNs from
CY7C1257AV18 to CY7C1257V18
CY7C1248AV18 to CY7C1248V18
CY7C1250AV18 to CY7C1250V18
Changed t
TH
and t
TL
from 40 ns to 20 ns, changed t
TMSS
, t
TDIS
, t
CS
, t
TMSH
,
t
TDIH
, t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns to 10 ns in TAP
AC Switching Characteristics table
Modified Power-Up waveform
*B
497628
See ECN
NXR
Changed the V
DDQ
operating voltage to 1.4V to V
DD
in the Features section,
in Operating Range table and in the DC Electrical Characteristics table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Changed V
REF
(Max.) spec from 0.85V to 0.95V in the DC Electrical
Characteristics table and in the note below the table
Updated foot note #17 to specify Overshoot and Undershoot Spec
Updated
Θ
JA
and
Θ
JC
values
Removed x9 part and its related information
Updated footnote #24
*C
1093183
See ECN
VKN
Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed I
DD
values from 925 mA to 1210 mA for 375 MHz, 800 mA to 1080
mA for 333 MHz, 725 mA to 1000 mA for 300 MHz
Changed I
SB
values from 290 mA to 320 mA for 375 MHz, 270 mA to 300
mA for 333 MHz, 250 mA to 290 mA for 300 MHz
Changed
Θ
JA
value from 12.43 °C/W to 16.25 °C/W
Changed t
CYC
max spec to 8.4 ns for all speed bins
Updated Ordering Information table
REV.
ECN No.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1250V18-375BZC | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-375BZI | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-375BZXC | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1250V18-375BZXI | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1257V18 | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1250XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1262XV18-366BZXC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 366MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1262XV18-450BZXC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 450MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12631KV18-400BZI | 功能描述:靜態(tài)隨機存取存儲器 2Mb X 18 400MHz QDR-II+ 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1263KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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