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參數(shù)資料
| 型號(hào)： | CY7C1231H-133AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| 中文描述： | 128K X 18 ZBT SRAM, 6.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 515K |
| 代理商： | CY7C1231H-133AXI |
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL Architecture
CY7C1231H
Cypress Semiconductor Corporation
Document #: 001-00207 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 26, 2006
Features
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
128K x 18 common I/O architecture
3.3V core power supply
3.3V/2.5V I/O operation
Fast clock-to-output times
— 6.5 ns (133-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed write
Asynchronous Output Enable
Offered in JEDEC-standard lead-free 100-pin TQFP
package
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency (NoBL) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
ZZ
OE
READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
SLEEP
CONTROL
Logic Block Diagram
[+] Feedback
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