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參數資料
| 型號： | CY7C1176V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 18兆位的國防評估報告⑩- II SRAM的4字突發(fā)架構（2.5周期讀寫延遲） |
| 文件頁數： | 10/29頁 |
| 文件大?。?/td> | 956K |
| 代理商： | CY7C1176V18 |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 10 of 29
Application Example
Figure 1
shows four QDR-II+ used in an application.
Figure 1. Application Example
Truth Table
The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.
[3, 4, 5, 6, 7, 8]
Operation
K
RPS WPS
DQ
DQ
DQ
DQ
Write Cycle
: Load
address on rising edge of
K; input write data on two
consecutive K and K rising
edges.
L-H
H
[9]
L
[10]
D(A) at K(t + 1)
↑
D(A + 1) at K(t + 1)
↑
D(A + 2) at K(t + 2)
↑
D(A + 3) at K(t + 2)
↑
Read Cycle
(2.5 Cycle
Latency): Load address on
rising edge of K; wait one
and a half cycle; read data
on two consecutive K and
K rising edges.
L-H
L
[10]
X
Q(A) at K(t + 2)
↑
Q(A + 1) at K(t + 3)
↑
Q(A + 2) at K(t + 3)
↑
Q(A + 3) at K(t + 4)
↑
NOP
: No operation.
L-H
H
H
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby
: Clock stopped.
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Vt
Vt
Vt
R
R
CLKIN/CLKIN
D
A
K
SRAM #4
RQ = 250
ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
A
K
SRAM #1
RQ = 250
ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
R = 50ohms, Vt = DDQ
R
Notes
2. The above application shows four QDR-II+ being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
4. Device powers up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively succeeding
the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1176V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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