型號(hào): CY7C1176V18-333BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁(yè)數(shù): 3/29頁(yè)
文件大?。?/td> 956K
代理商: CY7C1176V18-333BZXC
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 3 of 29
Logic Block Diagram (CY7C1163V18)
Logic Block Diagram (CY7C1165V18)
2
CLK
Gen.
A
(17:0)
K
K
Control
Logic
Address
Register
D
[17:0]
R
Read Data Reg.
RPS
WPS
BWS
[1:0]
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
V
REF
W
Write
Reg
36
A
(17:0)
18
2
2
2
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
1
CLK
Gen.
A
(16:0)
K
K
Control
Logic
Address
Register
D
[35:0]
R
Read Data Reg.
RPS
WPS
BWS
[3:0]
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
V
REF
W
Write
Reg
72
A
(16:0)
17
1
1
1
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
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相關(guān)PDF資料
PDF描述
CY7C1176V18-333BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-300BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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