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參數(shù)資料
| 型號： | CY7C1061DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Static RAM |
| 中文描述： | 16兆位（1米× 16）靜態(tài)RAM |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 401K |
| 代理商： | CY7C1061DV33 |
PRELIMINARY
CY7C1061DV33
Document #: 38-05476 Rev. *C
Page 4 of 10
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
–
10
Unit
Min.
Max.
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use
output loading shown in part a) of the AC test loads, unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
values until the first memory access can be performed.
7. t
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal Write time of the memory is defined by the overlap of CE
LOW (CE
HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the Write.
10.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
V
CC
(typical) to the first access
[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[7]
CE
1
LOW/CE
2
HIGH to Low-Z
[7]
CE
1
HIGH/CE
2
LOW to High-Z
[7]
CE
1
LOW/CE
2
HIGH to Power-Up
[8]
CE
1
HIGH/CE
2
LOW to Power-Down
[8]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
100
10
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
3
10
5
1
5
3
5
0
10
5
1
5
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[7]
WE LOW to High-Z
[7]
Byte Enable to End of Write
10
7
7
0
0
7
5.5
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
7
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