參數(shù)資料
型號： CY7C1061DV33-10ZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 16-Mbit (1M x 16) Static RAM
中文描述： 1M X 16 STANDARD SRAM, 10 ns, PDSO54
封裝： LEAD FREE, TSOP2-54
文件頁數(shù)： 3/10頁
文件大?。?/td> 401K
代理商： CY7C1061DV33-10ZXI
PRELIMINARY
CY7C1061DV33
Document #: 38-05476 Rev. *C
Page 3 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
CC
Relative to GND
[2]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Range
Ambient
Temperature
–40
°
C to +85
°
C
V
CC
Industrial
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
[7]
–
10
Unit
V
V
V
V
μ
A
μ
A
mA
mA
Min.
2.4
Max.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current V
CC
= Max., f = f
MAX
= 1/t
RC,
I
OUT
= 0 mA CMOS levels
Automatic CE Power-down
Current —TTL Inputs
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Automatic CE Power-down
Current —CMOS Inputs
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V, f = 0
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
0.4
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
125
30
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
CE
2
<= V
IL,
Max. V
CC
, CE > V
IH
I
SB2
CE
2
<= 0.3V, Max. V
CC
, CE > V
CC
– 0.3V,
25
mA
Capacitance
[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
TSOP II
6
8
VFBGA
8
10
Unit
pF
pF
C
IN
C
OUT
T
A
= 25
°
C, f = 1 MHz, V
CC
= 3.3V
Thermal Resistance
[3]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
All-Packages
TBD
TBD
Unit
°
C/W
°
C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
Thermal Resistance (Junction to Case)
four-layer printed circuit board
AC Test Loads and Waveforms
[4]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(d)
R1 317
R2
351
Rise time > 1 V/ns
Fall time:
> 1 V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
High-Z characteristics:
(a)
Notes:
2. V
(min.) = –2.0V and V
(max) = V
+ 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). 100
μ
s (t
power
) after reaching the minimum
operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
[+] Feedback
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