參數(shù)資料
型號: CY7C1061AV33-12BAI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 1M x 16 Static RAM
中文描述: 1M X 16 STANDARD SRAM, 12 ns, PBGA60
封裝: 8 X 20 MM, 1.20 MM HEIGHT, FBGA-60
文件頁數(shù): 5/11頁
文件大?。?/td> 269K
代理商: CY7C1061AV33-12BAI
PRELIMINARY
CY7C1061AV25
Document #: 38-05331 Rev. **
Page 5 of 11
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[6]
WE LOW to High-Z
[6]
Byte Enable to End of Write
6
0
0
6
5
0
3
7
0
0
7
8
0
0
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
0
3
5
5
6
6
7
8
AC Switching Characteristics
Over the Operating Range (continued)
[4]
Parameter
Description
-8
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Data Retention Waveform
2.3V
2.3V
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
. CE2 = V
IH
.
11.
WE is HIGH for Read cycle.
Read Cycle No. 1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
[10, 11]
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