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參數(shù)資料
| 型號： | CY7C1049BNV33-20VXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 20 ns, PDSO36 |
| 封裝： | 0.400 INCH, LEAD FREE, SOJ-36 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 420K |
| 代理商： | CY7C1049BNV33-20VXI |
CY7C1049BNV33
Document #: 001-06432 Rev. **
Page 5 of 8
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[15, 16]
Write Cycle No. 2 (WE Controlled, OE LOW)
[16]
Truth Table
CE
OE
WE
I/O
0
– I/O
7
Mode
Power
H
X
X
High Z
Power-Down
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
High Z
Selected, Outputs Disabled
Notes:
15.Data I/O is high-impedance if OE = V
.
16.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
17
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
17
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