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| 型號(hào)： | CY7C1049B-12VC |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 12 ns, PDSO36 |
| 封裝： | 0.400 INCH, SOJ-36 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | CY7C1049B-12VC |
CY7C1049B
Document #: 38-05169 Rev. *A
Page 4 of 10
Switching Characteristics
[4]
Over the Operating Range
7C1049B-12
Min.
7C1049B-15
Min.
7C1049B-17
Min.
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
5.
This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
power
time has to be provided initially before a read/write operation
is started.
6.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
Max.
Max.
Max.
Unit
V
CC
(typical) to the First Access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
1
12
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
17
12
15
17
3
3
3
12
6
15
7
17
8
0
0
0
6
7
7
3
3
3
6
7
7
0
0
0
12
15
17
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
15
12
12
0
0
12
8
0
3
17
12
12
0
0
12
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
8
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