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參數(shù)資料
| 型號(hào)： | CY7C1041DV33-12ZSXE |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 391K |
| 代理商： | CY7C1041DV33-12ZSXE |
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4-Mbit (256K x 16) Static RAM
CY7C1041DV33
Cypress Semiconductor Corporation
Document #: 38-05473 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 17, 2006
Features
Pin- and function-compatible with CY7C1041CV33
High speed
— t
AA
=10 ns
Low active power
— I
CC
= 90 mA @ 10 ns (Industrial)
Low CMOS standby power
— I
SB2
= 10 mA
2.0 V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in lead-free 48-ball VFBGA, 44-lead (400-mil)
Molded SOJ and 44-pin TSOP II packages
Functional Description
[1]
The CY7C1041DV33 is a high-performance CMOS Static
RAM organized as 256K words by 16 bits. Writing to the device
is accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then
data from I/O pins (I/O
0
–I/O
7
), is written into the location
specified on the address pins (A
0
–A
17
). If Byte HIGH Enable
(BHE) is LOW, then data from I/O pins (I/O
8
–I/O
15
) is written
into the location specified on the address pins (A
0
–A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
– I/O
7
. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
–I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041DV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K × 16
A
0
A
1
A
1
A
1
A
1
A
1
A
9
A
1
I/O
0
–I/O
7
OE
BLE
I/O
8
–I/O
15
CE
WE
BHE
[+] Feedback
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