
4-Mbit (256K x 16) Static RAM
CY7C1041D
PRELIMINARY
Cypress Semiconductor Corporation
Document #: 38-05472 Rev. *B
198 Champion Court
San Jose, CA 95134-1709
Revised July 29, 2005
408-943-2600
Features
Pin- and function-compatible with CY7C1041B
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 80 mA @ 10 ns (Commercial)
— I
CC
= 90 mA @ 10 ns (Industrial)
Low CMOS standby power
— I
SB2
= 10 mA
2.0 V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Lead-Free 44-Lead (400-Mil) Molded SOJ
V44 and 44-Pin TSOP II ZS44 packages
Functional Description
[1]
The CY7C1041D is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits. Writing to the device
is accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041D is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K x 16
A
0
A
1
A
1
A
1
A
1
A
1
A
9
A
1
I/O
0
–I/O
7
BLE
I/O
8
–I/O
15
OE
WE
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
SOJ
TSOP II
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
0
A
1
A
2
A
3
A
4
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
17
A
16
A
15
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
A
14
A
13
A
12
A
11
A
10
Selection Guide
7C1041D-10 7C1041D-12 7C1041D-15
10
12
80
75
90
85
10
10
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
15
70
80
10
Commercial
Industrial
Commercial/Industrial
Maximum CMOS Standby Current
mA
Note:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.